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In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written...
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In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half-selected cells. This study presents two schemes, one for single-ended and the other for differential sensing SRAMs, to eliminate the half-selection disturbance. In the first proposed scheme, the content of the desired row of the SRAM array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half-selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half-selection resilient schemes to 8 and 6 T SRAMs. Simulation results show that in the presence of radioactive particles, by applying their write-back scheme to 8 T SRAM and their read-before-write scheme to the conventional 6 T SRAM, the failure rate is reduced from an average of 56 and 20\%, respectively, to 0. The proposed schemes do not degrade write-ability of the SRAM cells, and are bit-addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.
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A universal-Vdd 32-KB four-way-set-associative embedded cache has been developed. The test cache chip was fabricated by using 0.18-Mm enhanced CMOS technology, and it was found to continuously operate from 0.65 V to 2.0 V. Its ope...
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A universal-Vdd 32-KB four-way-set-associative embedded cache has been developed. The test cache chip was fabricated by using 0.18-Mm enhanced CMOS technology, and it was found to continuously operate from 0.65 V to 2.0 V. Its operating frequency and power are from 120MHz and 1.7mW at 0.65 V to 1.04GHz and 530mW at 2.0 V. The cache is based on two new circuit techniques; a voltage-adapted timing-generation scheme with plural dummy cells for the wider-voltage-range operation; and use of a lithographically symmetrical cell for lower voltage operation.
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Over the last decades, the Symposium has been the premier forum for memory, putting more emphasis on seminal memory circuits rather than on record-setting performances with actually fabricated full chips, which has been the emphas...
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Over the last decades, the Symposium has been the premier forum for memory, putting more emphasis on seminal memory circuits rather than on record-setting performances with actually fabricated full chips, which has been the emphasis at the ISSCC. Indeed, it has been the breeding ground for DRAMs, SRAMs, flash memories, and other memories.
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Power-up states of static random-access memory (SRAM) memories are often used for generating physical unclonable functions (PUFs) in a variety of integrated circuits. The integrity of PUFs derived from commercial SRAM memories in ...
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Power-up states of static random-access memory (SRAM) memories are often used for generating physical unclonable functions (PUFs) in a variety of integrated circuits. The integrity of PUFs derived from commercial SRAM memories in radiation-prone environments has been recently recognized as an important problem and it remains an open issue. We perform both experimental evaluation and simulation analysis to quantify the effects of irradiation on the power-up state of commercial SRAM chips. Our results show that SRAM-PUF is significantly altered after irradiation, thus limiting its use in radiation-prone environments. The SRAM-PUF bit error rate (BER) increases monotonically with an increase in the total ionizing dose (TID), exceeding 15% after 100 krad(Si). We observe small annealing effects over time, but the BER remains high even five months after irradiation.
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In the context of mobile embedded devices, reducing energy is one of the prime objectives. Memories are responsible for a significant percentage of a system's aggregate energy consumption. Consequently, novel memories as well as n...
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In the context of mobile embedded devices, reducing energy is one of the prime objectives. Memories are responsible for a significant percentage of a system's aggregate energy consumption. Consequently, novel memories as well as novel-memory architectures are being designed to reduce the energy consumption. Caches and scratchpads are two contrasting memory architectures. The former relies on hardware logic while the latter relies on software for its utilization. To meet different requirements, most contemporary high-end embedded microprocessors include on-chip instruction and data caches along with a scratchpad. Previous approaches for utilizing scratchpad did not consider caches and hence fail for the contemporary high-end systems. Instructions are allocated onto the scratchpad, while taking into account the behavior of the instruction cache present in the system. The problem of scratchpad allocation is solved using a heuristic and also optimally using an integer linear programming formulation. An average reduction of 7% and 23% in processor cycles and instruction-memory energy, respectively, is reported when compared against a previously published technique. The average deviation between optimal and nonoptimal solutions was found to be less than 6% both in terms of processor cycles and energy. The scratchpad in the presented architecture is similar to a preloaded loop cache. Comparing the energy consumption of the presented approach against that of a preloaded loop cache, an average reduction of 9% and 29% in processor cycles and instruction-memory energy, respectively, is reported.
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Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high...
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Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32 nm metal-gate partially depleted SOI process technology, for low-voltage applications. Hardware exhibits a robust operation at 348 MHz and 0.5 V with a read and write power of 3.33 and 1.97 mW, respectively, per 4.5 KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6 V supply, an access speed of 1.2 GHz is observed.
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In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper...
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In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors' proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.
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The increasing sub-threshold leakage current levels with newer technology nodes has been identified by ITRS as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance impro...
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The increasing sub-threshold leakage current levels with newer technology nodes has been identified by ITRS as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size. This results in ever-increasing power per unit area and the accompanying problem of heat removal and cooling. Portable battery-powered applications, fuelled by pervasive and embedded computing, in the last few years have seen a tremendous growth and have reached a point where battery power can't be increased further. This raises the computational throughput per watt target for the future technology nodes. SRAM arrays which are used widely as a system component, such as caches and register files, in both high-performance and portable systems, are getting to be dominant power consumers because of their large capacity and area. Hence any reduction in cache energy can result in considerable overall power reduction. In this paper, we propose a novel circuit technique using depletion mode devices, to reduce the static energy of SRAM array in an on-chip cache by 90% without any performance impact.
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We have successfully demonstrated a misalignment-tolerant SRAM cell, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, w...
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We have successfully demonstrated a misalignment-tolerant SRAM cell, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, we have performed an intentionally misaligned experiment using a test structure with each SRAM block featuring a neighbor alignment-inspection mark. Moreover, utilizing the result of the experiment, we have created a manufacturing-friendly methodology of misalignment-limit determination.
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This work substantiates the impact of Gaussian doping on the electrical performance of double gate junctionless field-effect transistor (DG-JLFET). To get a better understanding of the influence of non-uniform doping, the device i...
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This work substantiates the impact of Gaussian doping on the electrical performance of double gate junctionless field-effect transistor (DG-JLFET). To get a better understanding of the influence of non-uniform doping, the device is compared with uniform-doped DG-JLFET with various concentrations. The device is later used to demonstrate its usability in six-transistor static random access memory (6T SRAM) bitcell by studying the performance metrics, i.e. stability noise margin and write delay. A comparison of performance metrics is also given with uniformly doped DG-JLFET-based-6T SRAM. Improvement in static noise margin was observed with Gaussian doping without compromising with write access time.
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